Current designers of electromagnetic or acoustic sensors are confronted by new problems related particularly to the great complexity of functions provided by the processing subassemblies that make up these systems. The complexity of these functions is as much due to the complexity of the operations implemented as to the great variation in the quantities of information (flows of information) processed from one operating phase of the system to another. Thus, one and the same function may have to process either a large-sized data stream or a very small-sized data stream. It may even have to process variable alternations of long data streams and short data streams. This implies, in particular, that for one and the same function the processing time can vary widely, this variability consequently giving rise to a degree of irregularity over the course of time in the data flows transmitted from one autonomous functional unit, or processing node, to another. Furthermore, the functions provided are more and more elaborate and entail computation loads of increasing size and sequencing operations of increasing complexity.
This present and especially future growth in desired performance levels is not very tolerant of conventional architectures around which current systems are designed, in particular. These architectures are generally based on the development of synchronous machines performing tasks which are admittedly autonomous but for which all of the sequencing is ensured by means of signals delivered by a specific processing node whose interchanges are tightly synchronized. Thus, the irregularity of the data flows makes developing such a processing node very difficult.
The effect of such architectures is to divide up systems designed in this manner into collections of subassemblies performing processing tasks, each subassembly being timed by a dedicated set of synchronization signals, provided by a subassembly, which is responsible for generating the various synchronization signals. They thus hinder a more integrated design step in which the system is considered as a whole to be a single multifunctional machine.
This dividing-up associated with excessive synchronism in the interchanges results in the system produced being limited in its processing capacity, in terms of the quantity of information processed. This limitation, which is directly attributable to the architecture adopted, hampers the necessary growth in the computation capacity of the systems, a growth that the processing nodes making up the subassemblies would, moreover, be capable of withstanding separately.
This limitation makes conventional architectures difficult to adopt for future systems for which the level of performance is directly related to the computation capacity and to the ability to adapt to variations in the data flows.
Another drawback of current architectures is related to the organization of the sequencing of the various processing nodes around a general sequencer which is responsible for overall synchronization and which supplies each of the other processing nodes with all of the synchronization signals which it requires. This centralized production of the synchronization signals is put into practice by the presence of a very large number of physical links in high-level systems, which makes the production and refinement of such systems tricky, and hampers their capacity for development.